The present invention concerns in general integrated digital systems and, more in particular, to a system in which streams of digital data from sources of different characteristics, asynchronous or of different bit rates, must be coordinately conveyed to an output channel. The invention is particularly though not exclusively useful in an interleaved synchronous memory.
In many applications the need may arise to organize a data flow at a certain bit rate in synchronization with an external clock under the control of an external systems controller. This may be done by combining together distinct data streams coming from internal asynchronous sources and/or having different bit rates.
Requirements of this kind are often encountered in data transmission systems where there may be a relatively broad band channel capable of operating at a relatively high speed, on which must be transmitted data coming from different sources. These different sources are relatively slower and often asynchronous. Another very peculiar example of such a system are interleaved synchronous memories.
The ATD (Address Transition Detection) signal recognizes a change of the address input by the external circuitry, and therefore, the new request of access and initiates a new read cycle. After enabling the sense amplifiers by the signal SAenable, an equalization of the sensing circuitry takes place. At the end of which, as timed by the signal EQZ, the effective reading of the memory cells takes place. Finally, after a certain interval of time that may vary from device to device, by way of a signal SAlatch, the recording of the read data into the latches in cascade to the sense amplifiers takes place, from where the read word may be transferred to the output buffers.
In memory devices designed for a synchronous read mode with a sequential type (burst) of access, the reading process exploits the fact that the reading takes place by successive locations. That is, the subsequent memory location to be read, and therefore, its address, is predictable from the address of the location being currently read.
A subgroup of these sequential (burst) synchronous read mode memories is represented by the interleaved memories. A burst access interleaved memory is described in U.S. Pat. No. 5,559,990, for example. In this type of memory, the cell array is divided in two semi-arrays or banks, each having its own read circuitry. The read streams of the two banks are thereafter superimposed according to one of the most commonly followed approaches. They are outphased, i.e., out of phase, from each other. While on one of the two banks or semi-array the steps of evaluation and transfer of the data to the output are being performed, on the other bank or semi-array (the next location to be addressed) a new read cycle may start without waiting for the conclusion of the current read cycle that involves the first semi-array.
In interleaved memories, a basic scheme of which is depicted in FIG. 1, the array is divided into two independent banks or semi-arrays, EVEN and ODD, respectively, each having its own independent read path. Typically, there are two counters (one for each bank) containing the address of the currently pointed memory location. In case of simultaneous reading processes evolving respectively on the two semi-arrays, the least significant bit of the address (A0) supports the multiplexing between the EVEN and the ODD banks. If A0=0, the data coming from the EVEN semi-array will be made available at the output. If A0=1, the data coming from the ODD semi-array will be made available at the output.
As it is commonly known, the reading of the two semi-arrays is carried out according to one of two different approaches. A first approach is simultaneous readings and multiplexing of the outputs. A second approach involves time readings that are out of phase.
According to the first approach, the readings are simultaneous on the two banks. The data read are stored in respective output registers and made available to the outside world in synchronization with an external clock signal. According to the second approach, the readings on the two semi-arrays have an alternate and interleaved evolution over time.
The first approach, though offering a simpler hardware implementation, limits the minimization of the start times of synchronous read cycles. For a better comprehension, it is necessary to consider the basic steps that are performed when passing from an asynchronous read mode to a synchronous read mode.
With reference to the scheme of FIG. 2, and starting the reading from an address X, the latter will be loaded on the EVEN bank counter and on the ODD bank counter, less the least significant bit (A0) of the address. The two counters will point to the same location X of the respective bank or semi-array.
If A0=0: the first read data is relative to the address X of the bank EVEN and the successive read data is the data X of the bank ODD.
If A0=1: the first read data is relative to the address X of the bank ODD and the successively read data is relative to the X+1 address of the bank EVEN.
In the first case, it is sufficient to perform a simultaneous reading of the two banks and multiplex the outputs. In the second instance, it is necessary to increment the counter before starting the reading on the bank EVEN.
Usually, known synchronous memory devices do not make any initial increment and wait for the successive cycle for incrementing both counters, and therefore, read the location X+1 of the banks EVEN and ODD. This makes the times of the first read cycle and of the second sequential read cycle at best equal to the asynchronous read mode time of the memory.
In general, it may be stated that the efficient management of the read processes has a direct influence of the performance of the memory device. Many read-path architectures have been proposed. Known read-path architectures have generally been conceived for responding efficiently to either one or the other of the two modes of operation: asynchronous or synchronous.
If a memory device is designed to be read in an asynchronous mode, it will be generally provided with a rather simple control circuitry for the read data streams. This allows the use of adaptive structures, such as dummy wordlines and dummy sense amplifiers, while leaving the reading circuitry free to evolve as fast as possible in order to achieve the shortest asynchronous access delays.
In contrast, in memory devices designed to function in a burst access mode or in a synchronous read mode, the possibility of making available in output a certain number of words read and stored in advance, permits, after a first asynchronous access, as long as it may be, a series of extremely fast read cycles. In this case though, the control logic must intervene extensively to manage the sense amplifiers which should not be left to evolve freely but be enabled, equalized and read at precise instants established by the control system. Prior European Patent Application Serial No. EP-98830801, filed on Dec. 30, 1998, and Italian Patent Application Serial No. MI99A00248, filed on Nov. 26, 1999, describe burst-mode EPROM devices with the above characteristics. These patent applications are both incorporated herein by reference in their entirety, and are assigned to the assignee of the present invention.
The access mode in a reading phase of operation is set to a specific protocol of use of two of the external protocol signals. These two signals are the address input latches enabling signal ALE and of the read stimulation signal RD.
The counters of the two semi-arrays, or the counter of the first bank and a more simpler register which functions as an address counter of the second bank, are incremented distinctly from one another. This is different from what is commonly done in interleaved memory devices. The readings are thus out of phase on the two banks from the first (asynchronous) read cycle. In this way, the memory device of the invention is perfectly able to switch to a synchronous mode reading phase at any time, which practically cuts in half the access time to such a mode.
The two different reading processes, according to an asynchronous random access mode and according to a synchronous burst access mode remain congruent with each other, having an alternate and interleaved evolution in time, as described in European Patent Application No. 00830068.3, filed on Jan. 31, 2000. This application is incorporated herein by reference in its entirety, and is assigned to the assignee of the present invention.
In view of the foregoing background and, more in general, with similar situations in which it would be advantageous to optimize the management of the data transfer within a system having sources of data of different bit rates and/or asynchronous, a circuit is provided to generate an output data stream synchronous with a certain clock provided by an external system controller.
A control circuit for managing transferring of data within a system is provided. The system preferably comprises a plurality of data sources for providing an output data stream synchronous with an external timing signal, an output register for storing data available at an output of the system, and a selection multiplexer for transferring the data from the plurality of data sources to the output register.
The control circuit may comprise a plurality of circuit blocks, with each circuit block being dedicated to one of the plurality of data sources and comprising a detection circuit for detecting availability of the data at an output of a selected data source, and a conditioned update path connected to the detection circuit for providing an update flag. A logic gate having a first input for receiving the update flag and a second input for receiving an output signal from the detection circuit may provide a selection signal for the selection multiplexer.
The system may further comprise an external data line connected to the output of the system, and an output buffer connected between the output register and the external data line. The control system may also include a pass-gate for coupling an input of the output buffer to the output register. The pass-gate is preferably enabled by the output signal from a respective detection circuit.
The conditioned update path preferably may include a first bistable circuit for providing a first flag for enablement of the updating, an enable detection circuit having a first input connected to the first bistable latch for receiving the first flag, and a second bistable circuit connected to the enable detection circuit for providing the update flag.
In one embodiment of the present invention, the plurality of data sources are asynchronous. In another embodiment of the present invention, the plurality of data sources have different bit rates.